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mp8715 100% duty cycle synchronous 4a, 21v, 500khz step-down converter mp8715 rev. 1.01 www.monolithicpower.com 1 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. the future of analog ic technology description the mp8715 is a 500 khz fixed-frequency pwm synchronous step-down regulator. mp8715 operates from a 4.5v to 21v input and generates an output voltage form 0.8v to v in with 100% duty cycle operation. the mp8715 integrates a 120m ? high-side switch and a 50m ? synchronous rectifier for high efficiency without an external schottky diode. it offers a very compact solution to achieve 4a continuous output current over a wide input supply range with excellent load and line regulation. external soft start and power good indication meet flexible design requirement. the mp8715 is available in a space saving 8- pin soic package with an exposed pad and 3mmx4mm 14-pin qfn package. features ? 4a output current ? wide 4.5v to 21v input operation range ? 100% duty cycle support ? 120m ? /50m ? internal power mosfet ? all ceramic capacitor design ? up to 95% efficiency ? 500khz fixed switching frequency ? adjustable output from 0.8v to vin ? external soft-start ? frequency synchronization input ? power ok indicator ? internal compensation ? over current hiccup and thermal protection ? available in 8-pin soic package with an exposed pad and 14-pin qfn3x4 package applications ? cable emtas ? p/asic/dsp/fpga core and i/o supplies ? printers and lcd tvs ? digital set top boxes ? network and telecom equipment ? point of load regulators all mps parts are lead-free and adhere to the rohs directive. for mps green status, please visit mps website under products, quality assurance page. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application 4 2 6 r2 10k mp8715 sw gnd fb en/sy nc bst vcc ss 4.5v-21v 1.2v/4a c3 100nf r1 4.99k rt 47k c5 10nf vin vin vout on/off 8 1 3 7 5 9 pok pok soic8e package efficiency v out =1.2v output current (a) 50 55 60 65 70 75 80 85 90 95 0 0.5 1 1.5 2 2.5 3 3.5 4 v in =21v v in =12v v in =5v
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 2 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. ordering information part number package top marking mp8715dn * soic8e mp8715 MP8715DL ** 3x4 qfn14 mp8715 * for tape & reel, add suffix ?z (e.g. mp8715dn?z); for rohs compliant packaging, add suffix ?lf (e.g. mp8715dn?lf?z) ** for tape & reel, add suffix ?z (e.g. MP8715DL?z); for rohs compliant packaging, add suffix ?lf (e.g. MP8715DL?lf?z) package reference absolute maxi mum ratings (1) vin??????????????-0.3v to 23v sw?? ?????-0.3v (-5v for <10ns) to 23v fb, ss????....??.. ???? ? 0.3v to +6.5v en/sync, pok, vcc.... ???? ? 0.3v to +6.5v bst to sw .................................. ? 0.3v to +6.5v continuous power dissipation (t a = +25c) (2) soic8e...................................................... 2.5w 3x4 qfn14 ................................................ 2.6w junction temperature...............................150c lead temperature ....................................260c storage temperature .............. ? 65c to +150c recommended operating conditions (3) input voltage v in ..............................4.5v to 21v output voltage v out ...........................0.8v to v in operating junction temp. (t j ). -40c to +125c thermal resistance (4) ja jc soic8e (exposed pad).......... 50...... 10 .. c/w 3x4 qfn14.......... ....................48...... 11 .. c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb. vin sw bst en/sync ss vcc pok fb 1 2 3 4 9 gnd 8 7 6 5 top view pin 1 id 14 13 12 11 10 9 8 ss gnd gnd gnd vcc pok fb in sw sw sw sw bst en/sync 1 2 3 4 5 6 7 top view exposed pad on backside soic8e 3x4 qfn14
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 3 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. electrical characteristics v in = 12v, t a = +25 c, unless otherwise noted. parameters symbol condition min typ max units supply current (quiescent) i q v en = 2v, v fb = 1v 0.66 ma shutdown current i in v en = 0v 1 a in undervoltage lockout threshold inuv vth rising edge 3.8 4.0 4.2 v in undervoltage lockout hysteresis inuv hys 880 mv vcc regulator v cc 5.1 v vcc load regulation i cc =5ma 5 % regulated fb voltage v fb t a = +25c 0.789 0.805 0.821 v fb input current i fb v fb = 0.85v 50 na en rising threshold v en_rising t a = +25c 1.05 1.6 en threshold hysteresis v en_hys 350 mv v en =2v 2 a en input current i en v en =0v 0 a en turn off delay en td-off 5 s soft-start current i ss v ss =0 5 a high-side switch on-resistance hs rds-on 120 m ? low-side switch on-resistance ls rds-on 50 m ? sw leakage current sw lkg v en = 0v, v sw = 0v or 12v 0 1 a bst under voltage lockout threshold bstuv vth 2.8 v high-side switch current limit (5) hsi limit sourcing 5 7 a low-side switch current limit lsi limit sinking 2 a oscillator frequency f sw 400 500 600 khz fold-back frequency f fb 0.25 f sw minimum on time t on-min 70 ns maximum duty cycle d max 100 % sync frequency range f sync 0.3 2 mhz
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 4 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. electrical characteristics (continued) v in = 12v, t a = +25 c, unless otherwise noted. parameters symbol condition min typ max units power ok rising threshold pok vthlh 0.90 v fb power ok falling threshold pok thhl 0.85 v fb pok output voltage low i pok_l i sink = 5ma 0.4 v pok leakage current i pok_leak v pg =3.3v 10 na internal charge pump current i charge_pump 90 a thermal shutdown threshold t sd rising 150 c thermal shutdown hysteresis t hys 20 c note: 5) guaranteed by design
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 5 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. pin functions soic8e pin# 3x4 qfn14 pin # name description 1 1 vin supply voltage. the mp8715 operates from a +4.5v to +21v input rail. c1 is required to decouple the input rail. use wide pcb traces and multiple vias to make the connection. 2 2,3,4,5 sw switch output. it is the source of high-side power device. 3 6 bst bootstrap. this capacitor is neede d to drive the power switch?s gate above the supply voltage. it is connected between sw and bst pins to form a floating supply across the power switch driver. an on-chip regulator and charge pump are both used to charge up the external boot-strap capacitor. 4 7 en/sync en=1 to enable the mp8715. external clock can be applied to en pin for changing switching frequency. for automatic start-up, connect en pin to vin with 100k ? resistor. 5 8 fb feedback. an external resistor divi der from the output to gnd, tapped to the fb pin, sets the output voltage. to prevent current limit run away during a short circuit fault condition the frequency fold-back comparator lowers the oscillator frequency when the fb voltage is below 400mv. 6 9 pok power good signal. when fb is less than 90% of 0.8v, pok is low. it is an open-drain output. use a high value pull- up resistor externally to pull it up to system power supply. 7 10 vcc bias supply. it?s the internal regulator output. decouple with 0.1f capacitor. 8 14 ss connect to an external capacitor used for soft-start. 9 11,12,13, exposed pad gnd ground (exposed pad, also serves as thermal pad)
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 6 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics v in =12v, v out =1.2v, l=1.8 h, t a =+25c, unless otherwise noted. load regulation input voltage (v) enabled supply current vs. input voltage peak current vs. duty cycle vcc regulator line regulation input voltage (v) input voltage (v) v cc voltage (v) line regulation load current (a) case temperature rise v out =5v input voltage (v) output current (a) 0 5 10 15 20 25 0 5 10 15 20 25 disabled supply current vs. input voltage 630 635 640 645 650 655 660 665 670 675 680 v fb =1v -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 v en =0v 3.5 4.0 4.5 5.0 5.5 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 5.5 6.0 6.5 7.0 7.5 8.0 10 20 30 40 50 60 70 80 peak current limit (a) -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0 5 10 15 20 25 i out =4a i out =2a i out =0a -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0 0.5 1 1.5 2 2.5 3 3.5 4 v in =21v v in =12v v in =5v 0 5 10 15 20 25 30 35 40 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 7 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics (continued) t a =+25c, unless otherwise noted. output current (a) efficiency v out =1.2v efficiency v out =3.3v efficiency v out =5v efficiency v out =1.8v output current (a) output current (a) output current (a) 50 55 60 65 70 75 80 85 90 95 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 v in =21v v in =12v v in =5v 50 55 60 65 70 75 80 85 90 95 v in =21v v in =12v v in =5v 50 55 60 65 70 75 80 85 90 95 100 0 0.5 1 1.5 2 2.5 3 3.5 4 50 55 60 65 70 75 80 85 90 95 100 v in =21v v in =12v v in =5v v in =21v v in =12v v in =7v
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 8 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1.2v, l=1.8 h, t a =+25c, unless otherwise noted. enable startup with 4a load load transient response i out =2a to 4a enable startup without load power up with 4a load v out 0.5v/div v sw 10v/div i inductor 5a/div v out 0.5v/div v sw 10v/div v pok 5v/div v en 5v/div i inductor 5a/div v out 0.5v/div v sw 10v/div v pok 5v/div v en 5v/div i inductor 5a/div v out 0.5v/div v sw 10v/div v pok 5v/div i inductor 5a/div short entry v out 0.5v/div v sw 10v/div i inductor 5a/div short recovery output ripple voltage i out =4a input ripple voltage i out =4a v sw 10v/div v in /ac 100mv/div power up without load v out 0.5v/div v sw 10v/div v pok 5v/div i inductor 2a/div v sw 10v/div v out /ac 10mv/div i inductor 2a/div v out /ac 50mv/div i out 2a/div i inductor 2a/div
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 9 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. block diagram hs driver vcc gnd fb ss en/sync in bst sw error amplifier pwm comparator current limit comparator current sense amplifer ls ilim comparator + - ls driver boost regulator vcc vcc charge pump regulator oscillator reference - + - + + - logic + - + 1meg pok pok comparator - + figure 1?functional block diagram
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 10 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. operation the mp8715 is a high frequency synchronous rectified step-down switch mode converter with built in internal power mosfets. it offers a very compact solution to achieve 4a continuous output current over a wide input supply range with excellent load and line regulation. the mp8715 operates in a fixed frequency, peak current control mode to regulate the output voltage. a pwm cycle is initiated by the internal clock. the integrated high-side power mosfet is turned on and remains on until its current reaches the value set by the comp voltage. when the power switch is off, it remains off until the next clock cycle starts. if, in whole of one pwm period, the current in the power mosfet does not reach the comp set current value, the power mosfet will work at 100% duty cycle. internal regulator most of the internal circuitries are powered from the 5.1v internal regulator. this regulator takes the vin input and operates in the full vin range. when vin is greater than 5.1v, the output of the regulator is in full regulation. when vin is lower than 5.1v, the output decreases, a 0.1uf ceramic capacitor for decoupling purpose is required. error amplifier the error amplifier compares the fb pin voltage with the internal 0.805v reference (ref) and outputs a current proportional to the difference between the two. this output current is then used to charge or discharge the internal compensation network to form the comp voltage, which is used to control the power mosfet current. the optimized internal compensation network minimizes the external component counts and simplifies the control loop design. enable/sync control en/sync is a digital control pin that turns the regulator on and off. drive en high to turn on the regulator, drive it low to turn it off. there is an internal 1meg resistor from en/sync to gnd thus en/sync can be floated to shut down the chip. 1) enabled by external logic h/l signal the chip starts up once the enable signal goes higher than en/sync input high voltage (2v), and is shut down when the signal is lower than en/sync input low voltage (0.4v). to disable the chip, en must be pulled low for at least 5s. the input is compatible with both cmos and ttl. 2) enabled by vin through voltage divider. connect en with vin through a resistive voltage divider for automatic startup as the figure 2 shows. en v in r en1 r en2 figure 2?enable divider circuit choose the value of the pull-up resistor r en1 and pull-down resistor r en2 to reset the automatic start-up voltage: en1 en2 in_start en_rising en2 (r r || 1m ) vv r||1m + =? where v en_rising is 1.12v en1 en2 in_stop en-falling en2 (r r || 1m ) vv r||1m = + ? where v en_falling is 0.9v the startup sequence is as below using the en divider. v cc-rising is the vcc uvlo rising threshold which is about 4.0v. vin en/sync vcc vout v en_rising 5us v en _ falling v in_start 1ms v cc_rising turn on delay turn off delay v in_stop figure 3?startup sequence using en divider 3) synchronized by external sync clock signal the chip can be synchronized to external clock range from 300khz up to 2mhz through this pin 2ms right after output voltage is set, with the
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 11 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. internal clock rising edge synchronized to the external clock rising edge. vin en/sync vcc vout clk 5us foldback 500khz external clk 0.625*vout_set 2ms 1ms vcc_rising vout_set figure 4?startup sequence using external sync clock signal under-voltage lockout (uvlo) under-voltage lockout (uvlo) is implemented to protect the chip from operating at insufficient supply voltage. the mp8715 uvlo comparator monitors the output voltage of the internal regulator, vcc. the uvlo rising threshold is about 4.0v while its falling threshold is a consistent 3.1v. power ok indicator when the fb is below 0.85vfb, the pok pin will be internally pulled low. when the fb is above 0.9vfb , the pok becomes an open-drain output. if pok function is not used, it can be left open. external soft-start the soft-start is implemented to prevent the converter output voltage from overshooting during startup. when the chip starts, the internal circuitry generates a soft-start voltage (ss) ramping up from 0v to 3.5v. when it is lower than the internal fb reference (ref), ss overrides ref so the error amplifier uses ss as the reference. when ss is higher than ref, ref regains control. the ss time can be set by external decoupled cap. the soft-start time can be calculated as below: ss 5 t(ms) vref(v) c (nf) 5a = to reduce the susceptibility to noise, do not leave ss pin open. use a capacitor with small value if you do not need soft function. over-current-protection and hiccup the mp8715 has cycle-by-cycle over current limit when the inductor current peak value exceeds the set current limit threshold. meanwhile, output voltage starts to drop until fb is below the under- voltage (uv) threshold, typically 30% below the reference. once a uv is triggered, the mp8715 enters hiccup mode to periodically restart the part. this protection mode is especially useful when the output is dead-short to ground. the average short circuit current is greatly reduced to alleviate the thermal issue and to protect the regulator. the mp8715 exits the hiccup mode once the over current condition is removed. thermal shutdown thermal shutdown is implemented to prevent the chip from operating at exceedingly high temperatures. when the silicon die temperature is higher than 150 c, it shuts down the whole chip. when the temperature is lower than its lower threshold, typically 130 c, the chip is enabled again. floating driver and bootstrap charging the floating power mosfet driver is powered by an external bootstrap capacitor. this floating driver has its own uvlo protection. this uvlo?s rising threshold is 2.5v with a hysteresis of 150mv. the bootstrap capacitor voltage is regulated internally by vin through d1, d2, m3, c4, l1 and c2 (figure 5). if (vin-vsw) is more than 5v, u2 will regulate m3 to maintain a 5v bst voltage across c4. d2 charge pump figure 5?internal bootstrap charging circuit startup and shutdown if both vin and en are higher than their appropriate thresholds, the chip starts. the
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 12 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. reference block starts first, generating stable reference voltage and currents, and then the internal regulator is enabled. the regulator provides stable supply for the remaining circuitries. three events can shut down the chip: en low, vin low and thermal shutdown. in the shutdown procedure, the signaling path is first blocked to avoid any fault triggering. the comp voltage and the internal supply rail are then pulled down. the floating driver is not subject to this shutdown command.
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 13 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. application information setting the output voltage the external resistor divider is used to set the output voltage (see typical application on page 1). the feedback resistor r1 also sets the feedback loop bandwidth with the internal compensation capacitor (see typical application on page 1). choose r1 to be around 40.2k ? for optimal transient response. r2 is then given by: out fb r1 r2 v 1 v = ? the t-type network is highly recommended when vo is low, as figure 6 shows. fb rt r1 r2 r6 c1 v out figure 6? t-type network table 1 lists the recommended t-type resistors value for common output voltages. table 1?resistor selection for common output voltages v out (v) r1 (k ? ) r2 (k ? ) rt (k ? ) r6 (k ? ) c1 (pf) l (h) c out (f) 1.05 4.99 16.5 47 0 15 1.8 222 1.2 4.99 10.2 47 0 15 1.8 222 1.5 4.99 5.76 47 0 15 2.2 222 1.8 4.99 4.02 33 0 15 2.2 222 2.5 40.2 19.1 10 0 27 3.3 222 3.3 40.2 13 4.99 0 33 3.3 222 5 40.2 7.68 3 0 47 4.7 222 note: the above feedback resistor table applies to a specific load capacitor condition as shown in t he table 1. other capacitive loading conditions will require different values. selecting the inductor a 1h to 10h inductor with a dc current rating of at least 25% percent higher than the maximum load current is recommended for most applications. for highest efficiency, the inductor dc resistance should be less than 15m ? . for most designs, the inductance value can be derived from the following equation. osc l in out in out f i v ) v v ( v l ? = where i l is the inductor ripple current. choose inductor ripple current to be approximately 30% if the maximum load current, 4a. the maximum inductor peak current is: 2 i i i l load ) max ( l + = under light load conditions below 100ma, larger inductance is recommended for improved efficiency. selecting the input capacitor the input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the ac current to the step-down converter while maintaining the dc input voltage. use low esr capacitors for the best performance. ceramic capacitors with x5r or x7r dielectrics are highly recommended because of their low esr and small temperature coefficients. for most applications, a 22f capacitor is sufficient. since the input capacitor (c1) absorbs the input switching current it requires an adequate ripple current rating. the rms current in the input capacitor can be estimated by: ? ? ? ? ? ? ? ? ? = in out in out load 1 c v v 1 v v i i the worse case condition occurs at v in = 2v out , where: 2 i i load 1 c = for simplification, choose the input capacitor whose rms current rating greater than half of the maximum load current. the input capacitor can be electrolytic, tantalum or ceramic. when electrolytic or tantalum capacitors are used, a small, high quality ceramic capacitor, i.e. 0.1 f, should be placed as close
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 14 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. to the ic as possible. when using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at input. the input voltage ripple caused by capacitance can be estimated by: ? ? ? ? ? ? ? ? ? = in out in out s load in v v 1 v v 1 c f i v selecting the output capacitor the output capacitor (c2) is required to maintain the dc output voltage. ceramic, tantalum, or low esr electrolytic capacitors are recommended. low esr capacitors are preferred to keep the output voltage ripple low. the output voltage ripple can be estimated by: ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? = 2 c f 8 1 r v v 1 l f v v s esr in out s out out where l is the inductor value and resr is the equivalent series resistance (esr) value of the output capacitor. in the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. the output voltage ripple is mainly caused by the capacitance. for simplification, the output voltage ripple can be estimated by: ? ? ? ? ? ? ? ? ? = in out 2 s out out v v 1 2 c l f 8 v v in the case of tantalum or electrolytic capacitors, the esr dominates the impedance at the switching frequency. for simplification, the output ripple can be approximated to: esr in out s out out r v v 1 l f v v ? ? ? ? ? ? ? ? ? = the characteristics of the output capacitor also affect the stability of the regulation system. the mp8715 can be optimized for a wide range of capacitance and esr values. pcb layout pcb layout is very important to achieve stable operation. please follow these guidelines and take figure 7, 8 for references. 4 layer pcb is recommended. 1) keep the connection of input ground and gnd pin as short and wide as possible. 2) keep the connection of input capacitor and in pin as short and wide as possible. 3) ensure all feedback connections are short and direct. place the feedback resistors and compensation components as close to the chip as possible. 4) route sw away from sensitive analog areas such as fb. 5) connect in, sw, and especially gnd respectively to a large copper area to cool the chip to improve thermal performance and long-term reliability. 6) adding rc snubber circuit from in pin to sw pin can reduce sw spikes.
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 15 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. 8 7 6 5 4 3 2 1 r3 rt c4 top layer inner1 layer gnd inner2 layer bottom layer figure 7?mp8715dn layout guide
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 16 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. bst sw sw sw sw en c2 c2 l1 c1 2 14 13 12 11 10 9 8 1 2 3 4 5 6 7 fb pok gnd gnd gnd vcc in r2 ss r3 top layer inner1 layer inner2 layer bottom layer figure 8?MP8715DL layout guide
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 17 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical application circuits (soic8e package) 1% 6.3v 25v 1% 5% 25v 25v 6.3v 4.5v - 21v c10 ns c4 c9 25v d1 ns c3 100nf r8 47k sw pok r1 4.99k 10 r7 c2b c2c c5 10nf r9 100k c6 15pf r2 10k vcc vin 1.2v/4a ns r4 r10 10 c1a gnd r5 4.7 c2a j1 c7 en r3 100k r6 0 l1 tp1 vout gnd 1 vin 3 bst 8 ss 5 fb 2 sw 9 gnd 4 mp8715dn 7 vcc 6 pok u1 figure 9? 1.2v output typical application schematic
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation mp8715 rev. 1.01 www.monolithicpower.com 18 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. package information soic8e (exposed pad) see detail "a" 0.0075(0.19) 0.0098(0.25) 0.050(1.27) bsc 0.013(0.33) 0.020(0.51) seating plane 0.000(0.00) 0.006(0.15) 0.051(1.30) 0.067(1.70) top view front view side view bottom view note: 1) control dimension is in inches. dimension in bracket is in millimeters. 2) package length does not include mold flash, protrusions or gate burrs. 3) package width does not include interlead flash or protrusions. 4) lead coplanarity (bottom of leads after forming) shall be 0.004" inches max. 5) drawing conforms to jedec ms-012, variation ba. 6) drawing is not to scale. 0.089(2.26) 0.101(2.56) 0.124(3.15) 0.136(3.45) recommended land pattern 0.213(5.40) 0.063(1.60) 0.050(1.27) 0.024(0.61) 0.103(2.62) 0.138(3.51) 0.150(3.80) 0.157(4.00) pin 1 id 0.189(4.80) 0.197(5.00) 0.228(5.80) 0.244(6.20) 14 85 0.016(0.41) 0.050(1.27) 0 o -8 o detail "a" 0.010(0.25) 0.020(0.50) x 45 o 0.010(0.25) bsc gauge plane
mp8715 ? 4a, 21v, 500khz, step down converter with 100% duty cycle operation notice: the information in this document is subject to change wi thout notice. please contact m ps for current specifications. users should warrant and guarantee that third party intellectual property rights ar e not infringed upon when integrating mps products into any application. mps will not assume any legal responsibility for any said applications. mp8715 rev. 1.01 www.monolithicpower.com 19 6/13/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. 3mm x 4mm qfn14 side view top view 1 14 8 7 bottom view 2.90 3.10 1.60 1.80 3.90 4.10 3.20 3.40 0.50 bsc 0.18 0.30 0.80 1.00 0.00 0.05 0.20 ref pin 1 id marking 1.70 0.50 0.25 recommended land pattern 2.90 note: 1) all dimensions are in millimeters. 2) exposed paddle size do es not include mold flash. 3) lead coplanarity sha ll be 0.10 millimeter max. 4) jedec reference is mo-229, variation vged-3. 5) drawing is not to scale. pin 1 id see detail a 3.30 0.70 pin 1 id option b r0.20 typ. pin 1 id option a 0.30x45 o typ. detail a 0.30 0.50 pin 1 id index area

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